logic gate
英 [ˈlɒdʒɪk ɡeɪt]
美 [ˈlɑːdʒɪk ɡeɪt]
n. 逻辑门，逻辑闸(以两种方式之一对所输入数据进行输出的电子开关)
牛津词典
noun
- 逻辑门，逻辑闸（以两种方式之一对所输入数据进行输出的电子开关）
an electronic switch that reacts in one of two ways to data that is put into it. A computer performs operations by passing data through a very large number of logic gates .
英英释义
noun
- a computer circuit with several inputs but only one output that can be activated by particular combinations of inputs
双语例句
- Each particle in the system acts like the logic gate of a computer.
系统中每个粒子的作用类似电脑里的逻辑闸。 - My paper design a Boolean logic gate by DNA computing.
本文就是利用DNA计算来设计布尔逻辑门。 - On the basis of operation rules of fuzzy number and of logic gate operator the probabilities of occurrence of middle events and top events were calculated, thus provided basis on enhancing the reliability design of system.
根据模糊数及逻辑门算子的运算规则，计算出了各中间事件及顶事件发生的概率，为提高系统的可靠性设计提供了依据。 - FPGA not only has the high logic gate array density and high reliability, but also has the user programmability of programmable logic devices.
FPGA既具有门阵列的高逻辑密度和高可靠性，又具有可编程逻辑器件的用户可编程性。 - Josephson junction logic gate
约瑟夫逊结逻辑门电路 - Generally speaking, the video codec in portable system can be realized by two ways: Pure software way of DSP ( digital signal processor) and pure hardware way of ASIC or FPGA ( programmable logic gate array).
一般来说视频编解码器在便携式系统上的实现有以下两种方式：纯软件的DSP（数字信号处理）方式、纯硬件的ASIC（专用集成芯片）或者FPGA（可编程逻辑门阵列）。 - This paper presents the conversion from dynamic logic gate to Markov chain, the solution of dynamic subtree top event failure probability and the method of obtaining the failure mode of subsystem using Markov model, that is sequence cutsets of the dynamic subtree.
论文研究了动态逻辑门向马尔可夫链的转化方法，利用马尔可夫链法求解动态子树顶事件概率，以及通过马尔可夫状态转移图直接找出子系统的故障模式和薄弱环节，即得到动态子树的顺序割集。 - The special Flip-Flop, combination logic gate and improved topology of Prescaler, enable the Prescaler to intensify the low power-high speed tradeoff.
其中，采用了特殊的D触发器和组合逻辑门结构，改进了预置数分频器结构，能够使分频器工作在低功耗、高速度之间有比较好的折衷。 - After study a series array multipliers algorithms and architectures,. the author design a high-performance multiplier in logic gate level, which using Booth and Wallace skill.
本文研究讨论了各种不同阵列乘法器的结构和原理，并完成了在门电路级设计了32位基4Booth编码并采用42压缩的Wallace高性能阵列乘法器电路。 - Based on the double parameter logic gate control, a new fuzzy control logic is presented and a two-stage fuzzy logic controller based on wheel angle acceleration is designed.
文中以双参数逻辑门限控制方法为基础提出了新的模糊控制逻辑，设计了基于车轮角加速度的两级模糊防抱控制器；